On semiconductor surfaces, the position of the Fermi level (EF) relative to its intrinsic value (Ei) may be significantly displaced from that in the bulk, resulting in bending of the electronic energy bands. This typically can occur when large densities of surface states, arising from unterminated bonds on the surface of the semiconductor, become occupied by carriers from the bulk because their energy is lower than the bulk Fermi level, or transfer carriers to the bulk if the surface states are occupied and at higher energy. The bands bend as the Fermi level at the surface comes into equilibrium with the bulk Fermi level, which can produce a strong internal electric field over the region of charge imbalance. In this situation, the Fermi level is considered “pinned” by surface states to its position at the surface. Surface fields and band bending can also result from trapped charge in oxide layers that are often deposited on surfaces to stabilize and protect them from the environment.
When band bending occurs along the sidewall of a diode, it can cause additional surface currents to flow under normal operating biases. Such additional current flowing in the diode is typically referred to as surface leakage. Surface leakage degrades performance in low signal level applications, such as photon sensing, because it contributes dark current and shot-noise that compete with the weak photocurrent signal. It can be particularly challenging for infrared (IR) sensors that detect photo-excited minority carriers because only a small amount of band bending is required in a narrow-gap sensor material to invert the surface and create a conducting channel that can allow carriers to bypass the junction or heterostructure barrier. The challenge is further increased in advanced infrared focal plane array applications that require smaller and smaller photodiode pixels for which the surface-to-volume ratio increases, and even small levels of surface leakage can easily become the dominant noise current.
In general, the discussion of structure designs herein, concerning both the prior art designs as well as exemplary embodiments of the disclosure, will focus on the example of an infrared heterojunction photodiode with a narrow-gap p-type absorber layer and an n-type surface channel. However, one of ordinary skill in the art will understand that the application can apply equally to the contrasting case of a diode structure with an n-type absorber and p-type inverted surface, and to photodiodes of similar architecture, but sensitive to shorter wavelengths of light. This application can also apply more generally to minority carrier heterostructure devices such as et photon-sensors that employ band offsets (barriers) instead of junctions to block majority carriers. For example, photo-sensors employing the nBn and analogous pBp geometries that are discussed below.
FIG. 1a is a schematic of a conventional photodiode mesa 100, which may be fabricated by etching the surrounding material to the bottom of the absorber region. For example, the mesa 100 may represent a single pixel within a photo diode array. Specifically, the conventional photodiode mesa 100 is an example of a heterojunction (HJ) infrared photodiode (IRPD) in which a narrow gap, moderately p-type (1016 cm−3) absorber layer 105 is adjacent to a wider gap lightly p-doped (2×1015 cm−3) semi-intrinsic layer (SIL) 110. The SIL, which typically has larger energy gap than the absorber, has the function of blocking the transport of majority carriers in the absorber region from flowing across the device to create a noise current. In the case of a photodiode with a p-n junction, the SIL is the depletion region, while in the case of the nBn and pBp structures that will be discussed below; the SIL is the barrier that blocks majority carriers from flowing between the absorber and the collecting contact. After a thickness equal to just over a depletion width, the wider gap layer 110 is then heavily n-doped to form the n+ cathode 115. FIG. 1a illustrates the exemplary layers and doping levels for the conventional photodiode 100 where an individual pixel is shown electrically isolated by single deep-etch isolation (SDEI) down to the bottom p+ contact layer 120, exposing the full cross-section of the diode structure on the mesa sidewalls. FIG. 1b is a plot of the bulk conduction and valence band edges for a conventional n/p photodiode mesa 100. Specifically, the ideal equilibrium conduction and valence band edges along the growth direction (z) are shown in FIG. 1b for the bulk of the conventional photodiode mesa 100, along with the position of the Fermi level EF in thermal equilibrium.
For many infrared detector materials of interest, such as those with a lightly p-type InAs/GaInSb superlattice (T2SL) absorber region, the exposed sidewalls typically have high densities of surface states that pin the Fermi level near the minority carrier band (the conduction band in this case). This creates an n-type surface inversion layer along each exposed sidewall. FIG. 2a is a schematic of a conventional photodiode mesa 200 illustrating the sidewall inversion layers, as indicated by the shaded regions 205. As a result of the surface inversion, the device 200 is essentially unipolar near the surface and surface electrons can flow nearly unimpeded in either direction across the junction. FIGS. 2b and 2c are plots of the bulk and surface conduction and valence band edges for the conventional photodiode mesa 200, which illustrate the effect of the sidewall inversion layers. Specifically, FIG. 2b depicts the bandstructure along Path 1 (210) in the bulk, while FIG. 2c depicts the bandstructure along Path 2 (215) near the surface. The alignments in FIGS. 2b and 2c differ because the Fermi level is situated near the top of the valence band in the bulk, whereas it is situated near the bottom of the conduction band at the inverted surface.
Along Path 1 (210), well away from the sidewalls, the band diagram in FIG. 2b shows the device 200 to have the normal p-i-n bandstructure, and rectification by the diode suppresses current flow in reverse bias. However, along Path 2 (215), near the surface of the absorber where the Fermi level is pinned near the conduction band, the current flow is quite different. FIG. 2c indicates that at this location, electrons occupying the n-type inversion layer encounter very little obstacle before reaching the n+ cathode. Because the SIL is too narrow to form an appreciable space charge field, only a small barrier separates the electron sea in the cathode from that in the surface inversion layer of the absorber. This results in a low-resistance leakage path for electrons flowing in either direction that effectively short-circuits the junction.
Accordingly, in the exemplary embodiments of the disclosure described below, the purpose is to increase the path length within the SIL to interpose a large electron (in this case) barrier on the surface between the absorber and cathode layers to block the flow of electrons. Once the surface channels are effectively blocked using an exemplary embodiment of this disclosure, other excess dark current mechanisms, such as high generation-recombination rates and tunneling currents, may be addressed separately. It is also emphasized that whereas the experimentally observed suppression of leakage currents by the exemplary embodiment of this disclosure is consistent with the general framework of the surface leakage model discussed herein and illustrated in FIGS. 2b and 2c, the model itself has not been rigorously tested and confirmed, whereas the exemplary embodiments of this disclosure have been experimentally demonstrated to be effective regardless of the details of the physical model that ultimately explains its effectiveness.
In the prior art, the most direct way to reduce sidewall current from a surface inversion layer is to passivate the surface by terminating the dangling bonds with a stable and charge-neutral chemistry, followed by the deposition of a dense insulating material to protect and encapsulate the passivated surface. FIG. 3a is a schematic of a diode 300 with effective surface passivation and encapsulation mitigating the effects of surface states. A good example of a dense insulating material is given by the use of silicon dioxide on silicon, which has proven to be convenient and effective as both a passivant and encapsulant. Surface states, however, are unique to each semiconductor material, and typically require specific chemistries and procedures to effectively terminate dangling bonds and render the surface inactive. For complex multi-constituent materials, finding an appropriate passivation can be extremely challenging, and there is no guarantee that one exists. An example is the case of photodiodes employing either InAs/GaInSb or InAs/InAsSb T2SL absorbers, for which surface leakage currents remain a dominant source of excess dark current in devices with p-type absorbers despite numerous efforts to develop an effective surface passivation chemistry for those systems.
FIG. 3b is a schematic of a diode 305 illustrating an alternative method of reducing surface leakage by using gate electrodes, in the prior art. Specifically, FIG. 3b illustrates the suppression of surface inversion by using gate electrodes to apply an external field under a bias VG. In this method, gate electrodes can be deposited so as to cover the mesa sidewalls, but are prevented from contacting the semiconductor by the presence of an intervening dielectric layer. The dielectric in this case is not optimized for terminating surface states, but rather for electrical isolation to prevent current from flowing from the gate electrode into the semiconductor. A voltage source can be attached to the gate and referenced to the bottom p-contact, and a bias (VG) can be applied to the gate so as to induce an electric field that counters the band bending due to surface states, thereby preventing the formation of a surface channel. However, this method is very challenging to implement on small pitch photodiode arrays, since it requires the fabrication of isolated gate electrodes that conform to the sidewalls of the deep and narrow trenches between neighboring pixels. It also requires an additional source to provide a voltage typically many times that of the diode operating bias to produce an effective gating field. This can be a single voltage source when the gate electrodes are tied together, or many voltage sources if the pixels must be gated individually. Furthermore, the high gate bias serves to amplify the impact of defects or non-uniformities between pixels, degrading uniformity.
Previously, shallow etch mesa isolation (SEMI) has been used as an alternative method of controlling surface leakage, which can employ device and band structure engineering to mitigate the effects of surface states. FIG. 4a is a schematic of a SEMI mesa structure 400. This prior art approach applies to heterojunction photodiodes in which the narrow gap lightly p-type absorber layer is covered by a wider gap SIL that is designed to be slightly thicker than a depletion width, or about 300 nm in one representative example of structures employing InAs/GaInSb absorber layers. On top of the SIL, the wider gap layer is heavily n-doped and continues for another 200 nm to form the cathode at the top of the device structure. Individual photodiode pixels can then be defined by a shallow trench etch that terminates just past the bottom of the cathode layer so that only the cathode and the wider-gap SIL layers are exposed. Since the absorber layer remains buried, no narrow gap materials are exposed to a surface. This effectively suppresses surface leakage because the exposed surface of the wider gap layer is much less susceptible to inversion. In the regions of the surface outside the mesas, it is thus necessary that the surface of the SIL remain near intrinsic or lightly p-type, in which case it will present an electron barrier typically greater than 100 meV, equivalent to about half its bandgap. FIG. 4b is a plot of the bulk conduction and valence band edges for the SEMI mesa structure 400. Specifically, FIG. 4b is a plot of the bandstructure along Path 1 405, indicating the presence of an electron barrier >100 meV high due to the difference in Fermi level in the SIL and absorber.
On the other hand, if the SIL is n-type or its surface does become inverted, the entire surface can form a common n-type electrode and all the diodes are shorted together. The connection to the common p-contact at the bottom of the diodes is typically made using a peripheral trench along the edge of the die, many diffusion lengths away from individual devices so that it does not contribute to the dark current. The limitation of the SEMI arrangement, however, is that it can be susceptible to significant cross-talk between adjacent pixels in an array, since the narrow gap absorber layers in neighboring pixels are not electrically isolated from one another. As the center-to-center distance between pixels (pitch) continues to decrease in focal plane arrays, the ratio of absorber thickness to pixel pitch (aspect) ratio approaches unity can cause high levels of spatial cross-talk. This is where significant numbers of photo-excited minority carriers diffuse to neighboring pixels, strongly degrading the spatial resolution of the SEMI array. Furthermore, the SEMI approach is extremely limited in its applicability to dual band device structures.
Accordingly, there remains a need in the art for a process that reduces surface leakage currents in photodiodes while still effectively isolating neighboring pixels, and which can overcome other limitations of prior art designs.